1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method and circuit for driving a word line of a memory cell.
2. Description of the Related Art
Semiconductor memory devices use a boosting voltage VPP to compensate for loss caused by a threshold voltage Vt of a transistor. The boosting voltage VPP is used for word line drivers. Word line drivers apply the boosting voltage VPP to a word line, write data of a bit line without the loss caused by the threshold voltage Vt of an NMOS cell transistor in a memory cell, and completely transfer cell data to the bit line during a reading operation.
FIG. 1 is a diagram illustrating operation of a conventional word line driving method. Referring to FIG. 1, when a word line WL is enabled to a boosting voltage level VPP, a bit line BL and a complementary bit line /BL are charge-shared based on data of a memory cell connected to the word line WL and developed.
In more detail, at a period A1, during which the word line WL is disabled, the bit line BL and the complementary bit line /BL are pre-charged to a voltage level IVCarray/2, corresponding to half of an internal power voltage IVCarray used for a memory cell array block. At a period A2, during which the word line WL rises to the boosting voltage VPP level, for example, when the data of the memory cell has a logic high level, the bit line BL rises by about 100 mV from the voltage level IVCarray/2 and is charge-shared. At a period A3, during which the word line WL is fully enabled to the boosting voltage level VPP, the bit line BL is developed to a logic high level of the internal power voltage IVCarray and the complementary bit line /BL is developed to a logic low level of a ground voltage VSS. Thereafter, at a period A4, the word line WL is disabled to the ground voltage level VSS.
The boosting voltage VPP is a high voltage level IVCarray+Vtcell+α, which is the sum of the internal power voltage IVCarray, a threshold voltage of a memory cell transistor Vtcell, and a predetermined voltage α. As indicated, the word line WL experiences high stress during the period A3.
Current semiconductor processing technology results in a micro memory cell transistor, having a then gate oxide film and a short gate of the micro memory cell transistor. When the boosting voltage VPP is applied to the word line WL connected to the gate of a conventional memory cell transistor, the stress caused by the high voltage level of the word line may result in a failure of the memory cell. Therefore, extended use of memory devices deteriorates long-term reliability.
Accordingly, the word line stress caused by the high voltage level can be reduced if the time during which the boosting voltage VPP is applied to the word line WL is shorter, for example, than that shown with respect to the word line period A3.